Integrated circuits (ICs) include components such as transistors, diodes, and resistors, fabricated in surface layers of semiconductor substrates. These components are connected by metal interconnects fabricated in layers above the substrates to form electronic circuits. Feature sizes of some components in state of the art ICs are less than 100 nanometers. It is common to fabricate ICs with several million transistors. Current ICs often include circuit blocks which are utilized in a plurality of IC designs.
Many ICs are designed using rules for placing and sizing interconnect features, such as width of metal lines and spaces between lines. Defects may occur during IC fabrication that cause electrical shorts between metal lines in close proximity that should be electrically isolated, or open circuits in metal lines that should be continuous. Practitioners of IC fabrication attempt to assess a level of defects for interconnects that are fabricated in a particular facility or facilities and designed using a particular set or sets of design rules. In addition, practitioners of IC fabrication attempt to identify design features that may be prone to short circuits or open circuits in high volume production. A common approach is to design a set of test circuits that reproduce various features of interest thousands or millions times in a test circuit, such that one defect among the placements of a given feature is detectable during electrical testing of the test circuits. Knowledge of defect levels for various features of interest and of features prone to short circuits or open circuits is often used by practitioners of IC fabrication to improve fabrication processes or design rules, or both.
A major shortcoming in commonly used approaches to assessing defect levels is that features in interconnect test circuits often fail to mimic features found in actual interconnects of commercial ICs. There are several phenomena behind this failure. Firstly, interconnects in commercial ICs include a multitude of configurations that defy characterization using basic structures such as line and space networks. Secondly, photolithographic processes that define interconnect patterns often generate unexpected artifacts in photoresist patterns of minimum sized features, making it difficult to design test circuits that evaluate worst case elements. Further, photolithographic processes often interact with existing interconnect levels in ICs in unpredictable ways, causing interconnect features in ICs to be formed differently than similarly designed features in test circuits which lack identical existing interconnect levels. Also, deposition and etching processes that form interconnect features are sensitive to loading effects, in that formed dimensions of an individual feature are functions not only of a photolithographic pattern of such feature, but also of average density of features in a vicinity of such feature. Loading effects of IC components are difficult to reproduce in interconnect test circuits. Lastly, designs of interconnect test circuits frequently do not provide useful information regarding physical locations of defects, which impedes efforts to isolate and analyze defect mechanisms for purposes of improving fabrication processes or design rules, or both.